The electronics industry is moving relentlessly toward a convergence of nanometer systems on a chip (SOCs). Leading-edge SOC designers, driven by wireless, networking, and multimedia consumer electronics, are using 0.18 micron processes and below to combine a variety of circuit types on the same large chip. Yet, the electronic design automation (EDA) industry's emphasis on front-end digital functionality verification has left design environments poorly equipped to handle the challenges of combing these massive, multi-million transistor circuits for electrical and parasitic effects. Designers find themselves trapped between the sheer size of these SOC designs and the complexity of electrical and parasitic effects that so heavily impact nanometer designs. Nevertheless, newer hierarchical circuit-level verification methods can deliver the high speed and accuracy needed for simulating and verifying full-chip post-layout circuit behavior.

In this new design world, most designs contain either analog or memory components, or both. RTL and gate-level simulators, emulators, and formal verification methods can no longer assist the designer adequately. These methods can't ensure mixed-signal SOCs' silicon success because of low-level electrical and parasitic effects such as crosstalk coupling noise, the inductance effect, and the electromigration concern and IR drop of the power net. Consequently, designers find themselves focusing more on the back-end and working harder to verify their SOCs with tools that are poorly matched to the task. For example, delay calculation with back annotation into Verilog provides a tried-and-true approach for verifying pure digital circuits.

At 0.18 micron and below, however, this digital approach might not be able to capture the nanometer electrical behavior important for high-speed and low-power digital circuits.

In the past, the EDA industry looked to mixed-level design approaches, where designers built and verified different circuit blocks at different levels of abstraction in an attempt to manage size and complexity. In SOC verification, these methods won't be sufficient because the high-level models will miss the details of most nanometer effects and inadequately predict timing and power behavior of the design.

Newer design tools are built upon a hierarchical database that uses memory more efficiently. Rather than storing multiple copies of the topologically equivalent components in the core memory repeatedly, hierarchical tools store a single template of each unique building component. They then instantiate from these templates multiple instances as needed to capture the entire design faithfully, using minimal memory storage.

They also typically come with a hierarchical solution engine that can complete simulation or analysis more efficiently than that performed by conventional flat database tools.

The new generations of hierarchical tools are showing to be highly flexible in their support for design methods. Rather than dictating a specific hierarchical verification strategy, these newer tools work with a designer's current methods. Designers can stay with conventional approaches-hierarchical pre-layout design and back annotation from extracted layout parasitics. In turn, newer hierarchical tools can work with extracted flat netlists and create hierarchy from the flat extracted netlist and can directly simulate extracted hierarchical netlists. The most promising approach relies on back annotation of extracted parasitics in DSPF format onto a pre-layout hierarchical netlist that is familiar and recognizable to designers. By working directly with the pre-layout hierarchical netlist, this last approach complements existing front-end design methods, yet also performs full-chip post-layout circuit-level verification needed for nanometer SOCs.

The convergence of SOC circuit types, the growing impact of analog operation and electrical and parasitic effects all point toward hierarchical circuit-level verification of the complete design as the key to design success. The new breed of hierarchical tools free designers from SPICE's capacity and performance restrictions and allow them to address full-chip post-layout verification, nanometer problem resolution, and performance optimization.

Sang Wang is CEO of Nassda Corp. (Mountain View, Ca). He was a senior vice president of Synopsys from 1997 to 1998. Prior to that he was a co-founder and CEO of EPIC Design Technology.